1. Field of the Invention
The present invention relates to a memory cell structure of a semiconductor memory such as a DRAM.
2. Description of the Background Art
FIG. 7 is a circuit diagram showing a memory cell structure of a background art DRAM. As shown in FIG. 7, a memory cell 1 comprises a memory transistor 2 that is an NMOS transistor, and a memory cell capacitor 3. The memory transistor 2 has a gate connected to a word line WL, a drain (source) connected to a bit line BL, and a source (drain) connected to a storage node serving as a first electrode of the memory cell capacitor 3. A fixed potential Vcp is applied to a cell plate serving as a second electrode of the memory cell capacitor 3.
A sense amplifier circuit 4 is provided between a pair of bit lines BL and BL. In a read operation, the sense amplifier circuit 4 detects and amplifies a potential difference between the pair of bit lines BL and BL.
FIG. 8 is a cross-sectional view of a memory cell region of the background art DRAM. FIG. 9 is a plan view of the memory cell region of the background art DRAM. The cross section of FIG. 8 is taken along the line B--B of FIG. 9.
As illustrated in FIGS. 8 and 9, MOS transistors 30 each including a gate electrode 11, a gate oxide film 12, sidewalls 13, a first source/drain region 27, a second source/drain region and a channel region are formed on a semiconductor substrate 10. Each of the MOS transistors 30 corresponds to the memory transistor 2 of FIG. 7. As shown in FIG. 9, the gate electrode 11 extending linearly is selectively formed, and functions also as the word line WL of FIG. 7.
The source/drain regions are formed in a diffusion region 50. Specifically, the first source/drain region 27 is formed in part of the diffusion region 50 which lies on one side of the gate electrode 11, and the second source/drain region not shown in FIG. 8 is formed in part of the diffusion region 50 which lies on the other side of the gate electrode 11. The term "source/drain" is used herein because this electrode sometimes functions as a source of carriers and sometimes functions to drain carriers to the outside, depending on whether information is read or written.
An interlayer insulation film 18 covers the MOS transistors 30, and a storage node 14 is formed on the interlayer insulation film 18 and the second source/drain region. As illustrated in FIG. 9, a region in which the storage node 14 contacts the second source/drain region serves as a storage node contact 52.
A capacitor dielectric film 15 is formed on the storage node 14. A cell plate 32 is formed over the entire surface of the semiconductor substrate 10 including the capacitor dielectric film 15 except on a region adjacent the surface of the first source/drain region 27.
An interlayer insulation film 21 is formed over the entire surface of the semiconductor substrate 10 including the cell plate 32. A bit line 33 extending linearly as shown in FIG. 9 is selectively formed on the interlayer insulation film 21. Part of the bit line 33 extends through the interlayer insulation film 21 and is formed directly on the first source/drain region 27. A region in which the bit line 33 contacts the first source/drain region 27 serves as a bit line contact 51. The bit line 33 corresponds to the bit line BL of FIG. 7.
An interlayer insulation film 22 is formed on the bit line 33, and an interlayer insulation film 23 is formed on the interlayer insulation film 22. A first aluminum interconnect line 31 for setting the potential of the gate electrode 11 (word line WL) is formed in the interlayer insulation film 23. An interlayer insulation film 24 is formed on the interlayer insulation film 23. A second aluminum interconnect line (not shown) is formed in the interlayer insulation film 24.
With such an arrangement, the read operation is performed in a manner described below. After the pair of bit lines BL and BL are precharged to the same potential (e.g., about one-half of a power supply voltage Vcc), the memory transistor 2 is turned on to electrically connect the memory cell capacitor 3 to the bit line BL. The potential of the bit line BL is increased or decreased based on the electric charge stored on the memory cell capacitor 3. The sense amplifier circuit 4 detects and amplifies the potential difference between the pair of bit lines BL and BL.
FIGS. 10 through 12 are cross-sectional views showing a background art method of manufacturing a memory cell of the DRAM shown in FIGS. 7 through 9.
With reference to FIG. 10, the MOS transistor 30 is selectively formed on the semiconductor substrate 10, and thereafter the interlayer insulation film 18 covers the upper surface of the gate electrode 11 of the MOS transistor 30. Then, the storage node 14 is selectively formed.
Next, as illustrated in FIG. 11, a nitride film is deposited and oxidized to form an oxynitride film which in turn is patterned to form the capacitor dielectric film 15. Doped polysilicon is deposited over the entire surface of the resultant structure and is then patterned (using a photolithographic technique or the like) so as to expose the surface of the first source/drain region 27, to form the cell plate 32.
With reference to FIG. 12, a high-temperature oxide film is deposited over the entire surface of the resultant structure and is then patterned (using a photolithographic technique or the like) so as to expose the surface of the first source/drain region 27, to form the interlayer insulation film 21. Thereafter, polysilicon is deposited over the entire surface of the resultant structure, and tungsten silicide (WSi) is formed on the polysilicon by a sputtering process. The polysilicon and tungsten silicide are patterned to form the bit line 33 directly connected to the first source/drain region 27.
Subsequently, an existing method is used to form the interlayer insulation films 22 to 24 and the first aluminum interconnect line 31. Thus, the structure shown in FIG. 8 is provided.
The manufacture of the background art DRAM constructed as above described requires at least four steps of wiring on the semiconductor substrate, i.e., the steps of forming the gate electrode (word line) of the MOS transistor, forming the storage node of the memory cell capacitor, forming the cell plate of the memory cell capacitor, and forming the bit line. This results in manufacturing costs higher than necessary.